Chemical mechanical polishing (CMP) is generally known in the art. For example U.S. Pat. No. 5,177,908 issued to Tuttle in 1993 describes a finishing element for semiconductor wafers, having a face shaped to provide a constant, or nearly constant, surface contact rate to a workpiece such as a semiconductor wafer in order to effect improved planarity of the workpiece. U.S. Pat. No. 5,234,867 issued 867 to Schultz et. al. in 1993 describes an apparatus for planarizing semiconductor wafers which in a preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer where a motor for rotating the platen and a non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. Fixed abrasive finishing elements are also known for polishing semiconductor layers. An example is WO 98118159 PCT application by Minnesota Mining and Manufacturing.
Semiconductor wafer fabrication generally requires the formation of layers of material having particularly small thicknesses. A typical conductor layer, such as a metallization layer, is generally 2,000 to 6,000 angstroms thick and a typical insulating layer, for example an oxide layer, is generally 3,000 to 5,000 angstroms thick. The actual thickness is at least partially dependent on the function of the layer along with the function and design of the semiconductor wafer. A gate oxide layer can be less than 100 angstroms thick while a field oxide is in the thousands of angstroms in thickness. In higher density and higher value semiconductor wafers the layers can be below 500 angstroms in thickness. Generally during semiconductor fabrication, layers thicker than necessary are formed and then thinned down to the required tolerances with techniques needed such as Chemical Mechanical Polishing. Because of the strict tolerances, extreme care is given to attaining the required thinned down tolerances. As such, it is important to accurately control the thinning of the layer during the thinning process and also as it reaches the required tolerances. The end point for the thinning or polishing operation is the final required tolerances. One current method to remove selected amounts of material is to remove the semiconductor wafer periodically from polishing for measurements such as thickness layer measurements. Although this can be done it is time consuming and adds extra expense to the operation. Further the expensive wafers can be damaged during transfer to or from the measurement process further decreasing process yields and increasing costs. Further, merely controlling finishing in a manner that stops polishing at the endpoint, misses the important aspect of controlling the polishing process itself where defects such as microscratches and other unwanted surface defects can occur. In fact, microscratches which are deep enough to penetrate the target surface can occur before the target surface depth is reached causing lower yields and lost product. Microscratches and other unwanted surface defects formed during polishing can adversely lower the polishing yield adding unnecessary expense to the polishing step in semiconductor wafer manufacture.
Confidential applicant evaluations show that the control of the finishing step is very complex. The chemical mechanical finishing step has multiple process control parameters. The manufacturing cost for the chemical mechanical finishing step is also complex. To effectively evaluate the cost of manufacture for a chemical mechanical finishing step requires the evaluation of multiple variables, and each with varying effects on the cost of manufacture. Further, some of the variables compete against each other. For instance, a higher finishing rate can lower some aspects of the cost of manufacture such as fixed costs but can also increase other aspects, such as reducing yields. Thus there is a need to evaluate in real time the effects on the cost of manufacture. Confidential analysis shows that there are some particularly preferred parameters of the cost of manufacture to use for real time process control of chemical mechanical polishing. Tracking the semiconductor wafer as it undergoes multiple polishing steps to update and change the manufacturing cost model used for effective cost control is unknown.
As discussed above, there is a need for an in situ control for a chemical mechanical polishing method which improves the cost of manufacture for a polishing step. There is a need for chemical mechanical polishing method which controls the operative finishing interface during polishing using a cost of manufacture model. There is a need for a cost of manufacture model which tracks the semiconductor wafer during its various polishing steps and uses a cost of manufacture model appropriate to that individual polishing step. There is a need for sensors which monitor the operative finishing interface in a manner that improves the ability to control and improve the cost of manufacture for a particular polishing step.
It is an advantage of this invention to develop is in an situ control subsystem which improves the cost of manufacture for a polishing step. It is an advantage of this invention to develop a finishing method which improves control of the operative finishing interface during polishing using a cost of manufacture model. It is an advantage of this invention to develop a method to use metrics related to cost of manufacture to improve control of the semiconductor wafer cost during its various polishing steps and to use this control to improve the manufacturing cost in situ at one or more individual finishing steps. It is an advantage of this invention to develop a preferred method which uses preferred sensors which monitor the operative finishing interface in a manner that improves the ability to control and improve the cost of manufacture for multiple and particular polishing steps.
These and other advantages of the invention will become readily apparent to those of ordinary skill in the art after reading the following disclosure of the invention.